Field of the Invention
The invention relates to a circuit for an electronic semiconductor module having interconnects which cross a specific region, a spine center, of the semiconductor module.
Various tests, also called test modes hereafter, are necessary in order to be able to test memory modules, for example dynamic random access memory (DRAMs). By way of example, the memory modules must be able to be brought to an extreme state with regard to the operating temperature and the operating voltage. What is achieved in the so-called burn-in test is that the memory module is already optimized by the manufacturer of the memory module with regard to the time duration until the occurrence of a fault (mean time between failures), that is to say the mean availability duration. Moreover, various parameters, such as critical timings, for example, must be able to be set during the production of the memory module. In a further test mode, a fault analysis can be affected in which parts of the memory module can be switched off. An additional test mode may be fast, efficient scanning of the memory cells in order to check the functionality thereof.
The test modes are achieved by extraordinary commands that are no longer necessary for the actual operation of the memory module. Therefore, test modes which set functions that are not available as standard are required for the comprehensive and efficient test of the memory module.
For these tests, the memory module is provided with interconnects. The latter are generally disposed beside further interconnects, which belong as data lines to the voltage supply and the signal-processing logic, on the memory module in such a way that they divide the latter into four quadrants. Each of the quadrants contains memory cells. In this case, the interconnects form a cross whose crossover region is also called a spine center hereafter. The control signals required for the test modes come from a central decoder circuit and are passed by a number of lines (metal lines or interconnects) from the central test mode circuit to their respective function block. Some also cross the spine center in this case. Mostly, however, the metal lines lying right at the top which run through the spine center delimit the chip area.
It is accordingly an object of the invention to provide a circuit for an electronic semiconductor module which overcome the above-mentioned disadvantages of the prior art devices of this general type, in which the area required for the wiring of the electronic semiconductor module and thus implicitly the total area of the electronic semiconductor module can be reduced.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit for an electronic semiconductor module. The circuit contains a specific region defining a first side and a second side, m interconnects crossing the specific region and having first ends and second ends, and n inputs disposed on the first side defined by the specific region. A number of the n inputs being greater than a number of the m interconnects. An encoder has inputs coupled to the n inputs and outputs connected to the first ends of the m interconnects. The encoder is disposed on the first side of the specific region. n outputs are provided and a decoder having inputs is connected to the second ends of the m interconnects and has outputs coupled to the n outputs. The decoder is disposed on the second side defined by the specific region.
The number of chips per wafer can advantageously be increased thereby.
The circuit according to the invention for an electronic semiconductor module has m interconnects which cross a specific region and has n inputs, which are disposed on one side of the region. In this case, the number n of inputs is greater than the number m of interconnects. An encoder is additionally provided, which is connected to the n inputs on the input side and to one end of the m interconnects on the output side and which is likewise disposed on one side of the region. A decoder, which is connected to the other end of the m interconnects on the input side and to n outputs on the output side, is disposed on the other side of the region.
It is advantageous that an edge detector is connected between the inputs and the encoder. As a result, if a level change occurs at the input of the edge detector, the edge detector generates a change in the signal level for a defined time duration.
A predecoder and an edge detector for the detection of positive edges are provided, which are connected between the inputs and the encoder. Therefore, even changes in the signal levels that occur simultaneously at the inputs can be processed.
A first switching and memory device is provided, which is connected to the outputs of the decoder on the input side.
A post-decoder is connected downstream of the decoder and a second switching and memory device is provided, which has an input connected to the output of the post-decoder. As a result, signals that are intended to be switched through simultaneously can also be processed.
The circuit according to the invention has a checking device for checking for simultaneity. If appropriate, it generates a control signal and feeds it to the encoder for coding. The decoder decodes the control signal and feeds it to the switching and memory device. The control signal can be used to signal that, if the semiconductor module is in the test mode, the test mode is now to be ended and left.
The checking device identifies a signal as a control signal when a plurality of signals at the inputs simultaneously change their state.
The edge detector has an input terminal, an output terminal and an exclusive-NOR element, the signal present at the input terminal of the edge detector being fed to the exclusive-NOR element undelayed in one instance and delayed in one instance, and the output of the exclusive-NOR element being connected to the output terminal of the edge detector.
The edge detector for the detection of positive edges has an input terminal, an output terminal and an AND element, the signal present at the input terminal of the edge detector being fed to the AND element undelayed in one instance and delayed in another instance, and the output of the AND element being connected to the output terminal of the edge detector for the detection of positive edges.
In the circuit, the encoder converts the n inputs to the m interconnects in a binary coded manner.
In the circuit, the first switching and memory device has a memory, the content of the memory changing with every second pulse of the signal present at the input of the first switching and memory device.
In the circuit, the second switching and memory device has a memory, the content of the memory being overwritten with each signal present at the input of the second switching and memory device, if an enable signal allows this.
In an advantageous manner, in the circuit according to the invention, different test modes can be set at the inputs by different addresses.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit for an electronic semiconductor module, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.